◎About

I build AI systems that learn continuously, reason under uncertainty, and run efficiently on real hardware — achieving 7.55× efficiency gains in neuromorphic streaming models and 5% accuracy improvements in Bayesian neural networks through novel Boosted Variational Inference methods.

I am a PhD candidate in Electrical Engineering at the University of South Florida, working in the Nano Computing Research Group under Dr. Sanjukta Bhanja. My research spans neuromorphic computing, probabilistic machine learning, and hardware-software co-design, with publications in Neurocomputing, ACM TECS, and IEEE venues.

Before the PhD, I worked as a software engineer at Cognizant, delivering banking solutions with $100K revenue impact — which gives me an enduring appreciation for systems that have to work in the real world, not just on benchmarks.

◈News

  • Mar 2026 Paper accepted at IEEE ISVLSI 2026 — "Near-Zero Multiplication Escape: A Framework for Sparse Deep Neural Networks Based on Racetrack Memory."
  • 2026 Multi-Agent Reflex Memory (MA-RM) paper under preparation for submission to Knowledge-Based Systems (Elsevier).
  • 2025 Selected for the ECEDHA Professional Development Award — national teaching leadership workshop funded by NSF.
  • 2025 Completed national active learning workshop "Creating an Interactive Classroom: Active Learning From Day One" through the iREDEFINE Program.
  • 2025 Organized and led LLM & AI Bootcamps for undergraduate STEM majors at USF, covering applied machine learning and large language models.
  • 2022 Founded the Graduate Engineering Communication Association (GECA) at USF, supporting bilingual and international STEM graduate students.

✶Research

Neuromorphic Sequence Modeling

HTM- and Reflex-Memory-based architectures for streaming anomaly detection and forecasting, achieving 7.55× efficiency gains over baseline implementations.

Bayesian Deep Learning

Boosted Variational Inference for uncertainty-aware neural networks, improving predictive accuracy by 5% on financial time-series with better posterior approximation.

Hardware-Conscious AI

Algorithm–hardware co-design using Domain Wall Memory and spintronic PIM as accelerators for neural workloads, bridging ML models with VLSI architectures.

▫Publications

  • Conference
    Near-Zero Multiplication Escape: A Framework for Sparse Deep Neural Networks Based on Racetrack Memory
    P. Bera et al. · IEEE ISVLSI 2026 · Accepted
    PDF coming soon
  • Preprint
    Quantification of Uncertainties in Probabilistic Deep Neural Network by Implementing Boosting of Variational Inference
    P. Bera, S. Bhanja · arXiv:2503.13909 · 2025
    arXiv
  • Journal
    Enhancing Biologically Inspired Hierarchical Temporal Memory with Hardware-Accelerated Reflex Memory
    P. Bera, S.H. Moon, J. Adorno, D.A. Reis, S. Bhanja · Neurocomputing · 2025
    DOI Scholar
  • Journal
    SPIMulator: A Spintronic Processing-In-Memory Simulator for Racetracks
    P. Bera, S. Cahoon, S. Bhanja, A. Jones · ACM Transactions on Embedded Computing Systems, 23(6) · 2024
    DOI Scholar
  • Conference
    Joint Pain Detection by Gait Analysis for Elderly Healthcare
    P. Bera, R. Kar, A. Konar · IEEE ICRCICN · 2015 · Cited 6×
    DOI Scholar
  • In prep
    Advancing Hierarchical Temporal Memory with Multi-Agent Reflex Memory
    P. Bera, J. Adorno, S. Bhanja · Targeting Knowledge-Based Systems (Elsevier)
    Manuscript in preparation

✺Projects

Multi-Agent Reflex Memory

Distributed anomaly detection framework where multiple Reflex-Memory agents coordinate over streaming data across finance, IoT, and transportation domains. Based on HTM experiments with multi-agent coordination.

HTM · Streaming · Agents · Anomaly Detection

GitHub →

SPIMulator

Simulator for Domain Wall Memory based processing-in-memory architectures, supporting matrix operations and neuromorphic workloads on spintronic devices. Developed in collaboration with the Jones Lab at Pitt.

DWM · PIM · Spintronics · Hardware

GitHub →

NLP Sentiment Pipeline

BERT-based NLP pipeline for sentiment classification on social media datasets, deployed as a real-time inference API end-to-end.

PyTorch · BERT · NLP · API

GitHub →

Boosted Variational BNNs

Bayesian neural networks with boosted variational inference for improved posterior approximation, with calibrated uncertainty on financial time-series.

PyTorch · Bayesian · Uncertainty · Time-series

GitHub →

Monte Carlo Photon Simulation

Monte Carlo simulation predicting photon pathways through human tissue, modeling photon-tissue interactions for biomedical and optical applications such as imaging and diagnostics.

Monte Carlo · Biomedical · Photonics · Python

GitHub →

◻Skills

Languages

Python C/C++ MATLAB SQL Verilog/FPGA Java

ML & AI

PyTorch TensorFlow Scikit-learn Bayesian NNs Transformers LLM Fine-tuning HTM.core Anomaly Detection

Hardware & Systems

CUDA Neuromorphic Computing Domain Wall Memory FPGA Design PIM Architectures

Cloud & Tools

AWS SageMaker Google Cloud Docker Kubernetes Git LaTeX Linux

◯Teaching

I design hands-on, inclusive learning environments bridging theory and practice. Selected for the national ECEDHA Professional Development Award (2025) and the NSF-funded iREDEFINE Program for teaching leadership in engineering.

  • Instructor of Record — Digital Logic Laboratory, USF (Jan 2023 – Present); 60+ students mentored across FPGA design and Verilog programming
  • Bootcamp Instructor — Data Science & AI/LLM Bootcamps for undergraduate STEM majors at USF
  • Founded GECA (Graduate Engineering Communication Association) — supporting bilingual and international STEM graduate students
  • Organized "AI for Everyone" workshops and Digital Logic Lab sessions for local high school students
  • Teaching Assistant — Digital Systems, Embedded Design, Computer Engineering (Aug 2019 – Dec 2022)

△Contact

I am happy to connect about research, collaborations, or interesting problems at the intersection of AI and hardware. Email is the best way to reach me.

Email: paviabera@usf.edu  ·  paviabera123@gmail.com

GitHub: github.com/paviabera

LinkedIn: linkedin.com/in/paviabera

Google Scholar: Pavia Bera